The Segmented Addrexx eXtension-Petranovic Architecture (SAX-PA) 4-bit
RISC CPU:
Welp, I spent a bunch of time on this and thought some random people I know
might be interested, so I put it up on the Web. I designed and implemented
this chip as part of the E157 class here at Mudd. Right now this page only
contains a block diagram of the CPU itself, but I plan to add some pictures
of the bread-boarded implementation and the full text of the quick and dirty
report I wrote on it.
Click here for an Acrobat version of the paper I wrote
on it (wheeee).
November 5, 1995 / toby@ovod-everett.org,
Return to my homepage.
